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- W2099295170 abstract "Abstract This paper describes the design of a very large scale integration (VLSI) application-specific integrated circuit (ASIC) for use in pattern recognition. The ASIC implements a moment invariant engine for use in real-time pattern recognition. The pattern recognition scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain, which effectively incorporated the carry lookahead (CLA) function into the adder cells. The prototype ASIC was fabricated in a 2.0 μm CMOS technology (simulated at 20 MHz) and was tested with 100% success to 16.67 MHz. The prototype consisted of a 4 × 8 multiplier and an 11-bit accumulator stage. The present ASIC design consists of a 9 × 26 multiplier (that has a maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 232.5 megaoperations/s [1024 × 1024 operations/s = 1 megaoperations/s (MOPs)] necessary to perform the moment invariant algorithms in real time on 512 × 512 pixel images with 256 gray scales." @default.
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- W2099295170 date "1993-01-01" @default.
- W2099295170 modified "2023-09-28" @default.
- W2099295170 title "Designing a custom VLSI moment invariant data signal processor" @default.
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- W2099295170 doi "https://doi.org/10.1016/0045-7906(93)90030-u" @default.
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