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- W2099301487 abstract "This paper describes a novel approach to scheduling with multiple supply voltages in the high-level synthesis of ASICs. In a significant shift from the existing scheduling algorithms for multiple voltages, the proposed approach considers, identifies, and exploits the maximal parallelism available in an initial schedule, and applies a modified stochastic evolution mechanism to iteratively improve, or re-schedule, the previously obtained best-schedule to reduce the maximal power consumption of function-units. Based on simulation and evaluation of the proposed approach (using standard benchmarks), it is observed that a power savings of up to 80% is possible when three supply voltage levels, 5 V, 3.3 V, and 2.4 V are considered. In addition to scheduling for low power, the proposed methodology can serve as a vital guiding tool to a designer for studying the efficacy of different design choices before a final design option is selected." @default.
- W2099301487 created "2016-06-24" @default.
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- W2099301487 date "2002-11-27" @default.
- W2099301487 modified "2023-10-07" @default.
- W2099301487 title "A novel scheduling-based CAD methodology for exploring the design space of ASICs for low power" @default.
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- W2099301487 doi "https://doi.org/10.1109/asic.1998.722814" @default.
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