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• W2099489306 abstract "A super-heterodyne receiver utilizing integrated high-Q filters to condition the desired signal to be digitized by a bandpass ADC at an IF of 110 MHz achieves a NF of 2.8 dB and an IIP3 of -8.4 dBm. The conventional M-phase filter is developed to a new form of high-Q filter that is centered at sum or difference of two clocks. The M-phase filter is also evolved to take two quadrature inputs to perform image rejection, while exhibiting a high-Q bandpass response with desired signal located in the center. Built of inverters, switches, and MOS capacitors, the receiver follows technology scaling and is reconfigurable through a clock. The receiver including the dividers and LO path draws 12 mA of battery current and occupies 0.76 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> in 65-nm CMOS." @default.
• W2099489306 created "2016-06-24" @default.
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• W2099489306 date "2011-12-01" @default.
• W2099489306 modified "2023-10-01" @default.
• W2099489306 title "A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-$Q$ Filters" @default.
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• W2099489306 doi "https://doi.org/10.1109/jssc.2011.2162909" @default.
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