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- W2099613658 abstract "Describes a new logic state model for gate level simulation based upon a powerset representation of the possible drive states at the output of a logic gate. Efficient implementation techniques for this model in a compiled-code logic simulator are presented, with the results that most complicated operations can be optimized into simple table lookups. Algorithmic issues in a multiple-strength multiple-delay logic simulator are discussed. Implementation results show that for typical circuits, compiled-code implementations of multiple-strength unit-delay logic simulation and multiple-strength multiple-delay logic simulation are slightly lower than three-state unit-delay simulation, and achieve speedups of 5 to 14 times compared to interpretive versions of the same algorithms.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2099613658 date "1993-01-01" @default.
- W2099613658 modified "2023-09-25" @default.
- W2099613658 title "A multiple-strength multiple-delay compiled-code logic simulator" @default.
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- W2099613658 doi "https://doi.org/10.1109/43.251157" @default.
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