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• W2099643334 abstract "<para xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme reduces the wordlength to 4 bits while lowering the error floor to below 10<formula formulatype=inline> <tex Notation=TeX>$^{-14}~$</tex></formula>BER. The proposed post-processor is conveniently integrated with the decoder, adding minimal area and power. The decoder architecture is optimized by groupings so as to localize irregular interconnects and regularize global interconnects and the overall wiring overhead is minimized. The <formula formulatype=inline><tex Notation=TeX>${hbox {5.35~mm}}^{2}$</tex></formula>, 65 nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput necessary for 10GBASE-T while dissipating 144 mW of power. </para>" @default.
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• W2099643334 date "2010-04-01" @default.
• W2099643334 modified "2023-10-02" @default.
• W2099643334 title "An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors" @default.
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• W2099643334 doi "https://doi.org/10.1109/jssc.2010.2042255" @default.
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