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- W2099730987 abstract "Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply." @default.
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- W2099730987 date "2003-10-02" @default.
- W2099730987 modified "2023-09-26" @default.
- W2099730987 title "A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS" @default.
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