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- W2100040971 abstract "This paper presents an architecture for implementing the H.264 Deblocking Filter with RGB output in FPGA, exceeding HDTV requirements when synthesized to a target FPGA. The goal of the design was to achieve the HDTV requirements, designing a deep pipelined architecture that makes a balanced use of the resources available in the target FPGA architecture. When synthesized to VirtexII-pro FPGA, the developed architecture used only 1800 logic cells and achieved 71 frames per second at 1080p HDTV resolution (1920x1080)." @default.
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- W2100040971 date "2007-10-01" @default.
- W2100040971 modified "2023-10-18" @default.
- W2100040971 title "An HDTV H.264 deblocking filter in FPGA with RGB video output" @default.
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- W2100040971 doi "https://doi.org/10.1109/vlsisoc.2007.4402519" @default.
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