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- W2100062112 abstract "We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accurately, our algorithms simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of our algorithm consists of a criticality history record of connection edges and a congestion map. This approach is applied to the 20 largest MCNC benchmark circuits. Experimental results show that compared with VPR [1], our algorithms yield an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of our algorithms is only 2.3X as of VPR's." @default.
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- W2100062112 date "2007-03-11" @default.
- W2100062112 modified "2023-10-15" @default.
- W2100062112 title "New timing and routability driven placement algorithms for FPGA synthesis" @default.
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- W2100062112 doi "https://doi.org/10.1145/1228784.1228918" @default.
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