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• W2100065418 abstract "A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage." @default.
• W2100065418 created "2016-06-24" @default.
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• W2100065418 date "2002-12-17" @default.
• W2100065418 modified "2023-09-28" @default.
• W2100065418 title "Hybrid design for testability combining scan and clock line control and method for test generation" @default.
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• W2100065418 doi "https://doi.org/10.1109/test.1994.527968" @default.
• W2100065418 hasPublicationYear "2002" @default.
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