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- W2100069175 abstract "With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors." @default.
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- W2100069175 date "2006-11-20" @default.
- W2100069175 modified "2023-09-24" @default.
- W2100069175 title "Verification Methodology for Self-Repairable Memory Systems" @default.
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- W2100069175 doi "https://doi.org/10.1109/ats.2006.87" @default.
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