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• W2100088734 abstract "This paper presents a novel 1Mb STT-MRAM for power and area reduction of cache memory in micro-processors. This memory adopts current-integral sensing scheme for high speed read, and uses advanced perpendicular STT-MRAM for high speed write to achieve 250 MHz operation, 17.8 mW read power and 46.5 mW write power per 256-b I/O. Using a processor simulator, it has been confirmed the total cache power is reduced, whereas those for STT-MRAMs previously reported are increased compared with that for SRAM." @default.
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• W2100088734 date "2013-06-11" @default.
• W2100088734 modified "2023-10-01" @default.
• W2100088734 title "A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors" @default.
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