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- W2100089592 abstract "The authors present an architecture for an 8-b*8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s. >" @default.
- W2100089592 created "2016-06-24" @default.
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- W2100089592 date "2003-01-02" @default.
- W2100089592 modified "2023-09-25" @default.
- W2100089592 title "A high-speed 8*8-bit CMOS parallel array processor" @default.
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- W2100089592 doi "https://doi.org/10.1109/secon.1992.202250" @default.
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