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• W2100090731 abstract "An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closed-loop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm2." @default.
• W2100090731 created "2016-06-24" @default.
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• W2100090731 date "2015-05-01" @default.
• W2100090731 modified "2023-10-17" @default.
• W2100090731 title "A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique" @default.
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• W2100090731 doi "https://doi.org/10.1109/iscas.2015.7168693" @default.
• W2100090731 hasPublicationYear "2015" @default.
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