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- W2100092576 abstract "Two different transconductance linearization schemes are studied. By means of a simple saturation model, the ideal linear input range for each one is obtained and a comparative study is carried out. Using a more accurate model, analytical expressions are derived that yield an efficient design strategy to reduce the second-order effects. One of these cells has been used to design a four-quadrant multiplier fabricated in a 2- mu m, 5-V process. An experimental linear input range of 1.4 V has been measured, showing the suitability of the circuit structure in a low-power process when the authors' strategy is used. >" @default.
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- W2100092576 date "2003-01-13" @default.
- W2100092576 modified "2023-10-01" @default.
- W2100092576 title "A study of linearizing techniques used in MOS analog multipliers" @default.
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- W2100092576 doi "https://doi.org/10.1109/iscas.1989.100627" @default.
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