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• W2100368733 abstract "In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2/sup m/), for values of m/spl les/8. A systolic array processor architecture has been developed by the authors for performing multiplication and division in GF(2/sup m/). A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip called ACE implementing the proposed algorithm for Galois field GF(2/sup 4/) based exponentiation has been designed and verified using CMOS 2-micron technology. The chip can yield a computational rate of 40 million exponentiations per second. >" @default.
• W2100368733 created "2016-06-24" @default.
• W2100368733 creator A5027665366 @default.
• W2100368733 creator A5063718916 @default.
• W2100368733 date "2002-12-17" @default.
• W2100368733 modified "2023-09-25" @default.
• W2100368733 title "ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation" @default.
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• W2100368733 doi "https://doi.org/10.1109/icvd.1994.282705" @default.
• W2100368733 hasPublicationYear "2002" @default.
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