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- W2100792386 abstract "This research presents core-based VLSI design for digital protective relays based on the generalized CORDIC processor. It has high-speed processing capability which is fully sufficient for parallel 12-channel sources at high sampling rate (256 samples per cycle). Required hardware can be quite reasonable in most ASIC technologies. Relaying accuracy is remarkably guaranteed through hardware exponentiation. It also provides re-programmability as in typical instruction set architectures for appropriate parameterization. The entire design was successfully built by 0.35 /spl mu/m CMOS technology with a the size of 5mm /spl times/ 5mm." @default.
- W2100792386 created "2016-06-24" @default.
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- W2100792386 date "2005-07-27" @default.
- W2100792386 modified "2023-10-12" @default.
- W2100792386 title "A Study on an ASIC Design Technique for Digital Protective Relays" @default.
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- W2100792386 doi "https://doi.org/10.1109/iscas.2005.1465485" @default.
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