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- W2100933266 abstract "A physics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM." @default.
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- W2100933266 date "2011-07-01" @default.
- W2100933266 modified "2023-09-25" @default.
- W2100933266 title "Viability Study of All-III–V SRAM for Beyond-22-nm Logic Circuits" @default.
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- W2100933266 doi "https://doi.org/10.1109/led.2011.2148092" @default.
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