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• W2100966314 abstract "Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance." @default.
• W2100966314 created "2016-06-24" @default.
• W2100966314 creator A5033891130 @default.
• W2100966314 creator A5059658485 @default.
• W2100966314 date "2003-04-01" @default.
• W2100966314 modified "2023-09-27" @default.
• W2100966314 title "Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures" @default.
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• W2100966314 doi "https://doi.org/10.1109/tvlsi.2002.801622" @default.
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