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• W2101004723 abstract "This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-¿m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ¿m <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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• W2101004723 date "2010-04-01" @default.
• W2101004723 modified "2023-10-12" @default.
• W2101004723 title "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure" @default.
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• W2101004723 doi "https://doi.org/10.1109/jssc.2010.2042254" @default.
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