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• W2101256601 abstract "This paper focuses on implementing a 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>s</sup> complement 8×8 dual-rail bit-wise pipelined multiplier using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18μm TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed." @default.
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• W2101256601 date "2007-04-01" @default.
• W2101256601 modified "2023-09-27" @default.
• W2101256601 title "Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2^S Complement Multiplier" @default.
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• W2101256601 doi "https://doi.org/10.1109/tpsd.2007.4380386" @default.
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