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- W2101406832 abstract "Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations." @default.
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- W2101406832 date "2003-01-20" @default.
- W2101406832 modified "2023-09-27" @default.
- W2101406832 title "Determining redundancy requirements for memory arrays with critical area analysis" @default.
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- W2101406832 doi "https://doi.org/10.1109/mtdt.1999.782683" @default.
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