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- W2101687630 abstract "Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complexity of modern embedded systems. TLM provides designers with high-level interfaces and communication protocols for abstract modeling and efficient simulation of system platforms. The Open SystemC Initiative (OSCI) has recently released the TLM-2.0 standard, to standardize the interface between component models for bus-based systems. The TLM standard aims at facilitating the interchange of models between suppliers and users, and thus encouraging the use of virtual platforms for fast simulation prior to the availability of register-transfer level (RTL) code. On the other hand, because a TLM IP description does not include the implementation details that must be added at the RTL, the process to synthesize TLM designs into RTL implementations is still manual, time spending and error prone. In this context, this paper presents a methodology for automating the TLM-to-RTL synthesis by applying the theory of high-level synthesis (HLS) to TLM, and proposes a protocol synthesis technique based on the extended finite state machine (EFSM) model for generating the RTL IP interface compliant with any RTL bus-based protocol." @default.
- W2101687630 created "2016-06-24" @default.
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- W2101687630 date "2010-06-01" @default.
- W2101687630 modified "2023-09-23" @default.
- W2101687630 title "Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs" @default.
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- W2101687630 doi "https://doi.org/10.1109/hldvt.2010.5496652" @default.
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