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- W2101701182 abstract "This paper presents a new systolic squarer and a new systolic exponentiator for GF(2/sup m/) with the standard basis representation. While computing squares in GF(2/sup m/), the proposed systolic squarer has smaller latency and less hardware requirement than a dedicated systolic multiplier. The proposed systolic exponentiator consists of [m/2] squarers, one multiplier, and [(m-1)/2] power-sum circuits (for AB/sup 2/+C). As compared to existing related exponentiators, it involves less hardware complexity and smaller latency. Both of the proposed architectures involve the features of regularity, modularity, and unidirectional data flow. As a consequence, they are well suited to VLSI implementation with fault-tolerant design." @default.
- W2101701182 created "2016-06-24" @default.
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- W2101701182 date "2002-11-22" @default.
- W2101701182 modified "2023-09-27" @default.
- W2101701182 title "A new systolic squarer and its application to compute exponentiations in GF(2/sup m/)" @default.
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- W2101701182 doi "https://doi.org/10.1109/iscas.1997.621557" @default.
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