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• W2102432039 abstract "Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed." @default.
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• W2102432039 date "2003-06-25" @default.
• W2102432039 modified "2023-09-24" @default.
• W2102432039 title "A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric" @default.
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• W2102432039 doi "https://doi.org/10.1109/isscc.2002.992979" @default.
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