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- W2102547814 abstract "Optimistic concurrency provided by Transactional Memory (TM) makes it a good candidate for maintaining synchronization in future multi-core processors. Speculative execution and bulk level conflict detection enable TM to provide synchronization at fine grain without the complexity of managing fine grain locks. Early hardware TM systems proposed to store the information needed for checking conflicts in the Level 1 (L1) cache, thereby limiting the size of a transaction to the size of the L1 cache. The introduction of signatures to TM systems removed this limitation and allowed transactions to be of any size." @default.
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- W2102547814 date "2012-05-15" @default.
- W2102547814 modified "2023-09-30" @default.
- W2102547814 title "SnCTM" @default.
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- W2102547814 doi "https://doi.org/10.1145/2212908.2212919" @default.
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