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- W2103017106 abstract "The paper focuses on the synthesis of a highly parallel reconfigurable hard- ware implementation for the International Data Encryption Algorithm (IDEA). Cur- rently, IDEA is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as military, requires efficient, highly re- liable and correct hardware implementation. We will stress the affordability of such requirements by adopting a methodology that develops reconfigurable hardware cir- cuits by following a transformational programming paradigm. The development starts from a formal functional specification stage. Then, by using function decomposition and provably correct data refinement techniques, powerful high-order functions are refined into parallel implementations described in Hoare's communicating sequen- tial processes notation(CSP). The CSP descriptions are very closely associated with Handle-C hardware description language (HDL) program fragments. This descrip- tion language is employed to target reconfigurable hardware as the final stage in the development. The targeted system in this case is the RC-1000 reconfigurable com- puter. In this paper different designs for the IDEA corresponding to different levels of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation are included." @default.
- W2103017106 created "2016-06-24" @default.
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- W2103017106 date "2004-01-01" @default.
- W2103017106 modified "2023-09-27" @default.
- W2103017106 title "Reconfigurable Hardware Synthesis of the IDEA Cryptographic Algorithm" @default.
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