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- W2103123048 abstract "A nested-PLL(NPLL) architecture for low-noise wide-bandwidth fractional-N frequency synthesizer is presented. In order to reduce the quantization noise of the fractional-N PLL, delta-sigma modulator(DSM) is clocked at nine times of the reference frequency. A band pass filter, implemented in form of a PLL, is added to reduce the noise folding. Prototype implemented in 0.13um CMOS process achieves 26dB quantization noise suppression while consuming 9.6mW and occupying 0.46mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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- W2103123048 date "2011-09-01" @default.
- W2103123048 modified "2023-09-27" @default.
- W2103123048 title "A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL" @default.
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- W2103123048 doi "https://doi.org/10.1109/cicc.2011.6055308" @default.
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