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- W2103161792 abstract "Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding sample/hold (S/H) circuit to replace residue amplifier. Simulated with SMIC O.35 mum/3.3 V AMS Si-CMOS process models, the results are shown that on the condition of realizing 250MSPS, the ADC achieves DNL<plusmn0.4LSB, INL<plusmn.5LSB, SFDR 59.2 dB at Nyquist frequency, only 85 mW power dissipation and 1.2times0.8 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> layout area. The ADC system architecture is to be employed in the field of high-speed low-power mixed-signal processing" @default.
- W2103161792 created "2016-06-24" @default.
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- W2103161792 date "2006-06-01" @default.
- W2103161792 modified "2023-09-24" @default.
- W2103161792 title "An 8-Bit 250MSPS Modified Two-Step ADC" @default.
- W2103161792 cites W2157692794 @default.
- W2103161792 doi "https://doi.org/10.1109/icccas.2006.285113" @default.
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