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- W2103228767 abstract "An evaluation of VHSIC hardware description language (VHDL) based design tools using synthesis vs. schematic capture-macrocell approach to field programmable gate array (FPGA) design is described. The risk of committing to an ASIC technology for a project that may or may not go into production can be mitigated by using FPGAs. Designing with VHDL allows flexibility if the decision is made to migrate the design. >" @default.
- W2103228767 created "2016-06-24" @default.
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- W2103228767 date "2003-01-02" @default.
- W2103228767 modified "2023-09-26" @default.
- W2103228767 title "Evaluating VHDL-based ASIC synthesis tools" @default.
- W2103228767 cites W2097497460 @default.
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- W2103228767 doi "https://doi.org/10.1109/asic.1992.270240" @default.
- W2103228767 hasPublicationYear "2003" @default.
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