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- W2103262808 abstract "GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8/spl times/2(MUX)/2/spl times/8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-/spl mu/m BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2103262808 date "1994-07-01" @default.
- W2103262808 modified "2023-09-27" @default.
- W2103262808 title "GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's" @default.
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- W2103262808 doi "https://doi.org/10.1109/4.303718" @default.
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