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• W2103263103 abstract "In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the dock skews produced by three algorithms (Partition. MST, Matching) [5] are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises." @default.
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• W2103263103 date "2007-11-05" @default.
• W2103263103 modified "2023-09-23" @default.
• W2103263103 title "Skew aware polarity assignment in clock tree" @default.
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• W2103263103 doi "https://doi.org/10.5555/1326073.1326151" @default.
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