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- W2103299967 abstract "Circuit optimization and design for a multi-bit rate fast transceiver for application of ISDN to SDSL rates (from 160 kb/s up to 2.3 Mb/s) is proposed. In the transmitter path is a sigma-delta time continuous multi-bit 14-bit DAC. It includes dynamic averaging for linearity improvement with simple filtering. The hybrid is also optimized using passive elements for the loop variations and with additional active filters for additional rejection. It is integrated for the simple reason of eliminating the high SNR requirement from the multi-bit sigma-delta ADC in the receive path (using AGC)." @default.
- W2103299967 created "2016-06-24" @default.
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- W2103299967 date "2003-01-20" @default.
- W2103299967 modified "2023-09-26" @default.
- W2103299967 title "Optimization and design of fast transceiver for DSL application in CMOS technology" @default.
- W2103299967 doi "https://doi.org/10.1109/icecs.1999.814425" @default.
- W2103299967 hasPublicationYear "2003" @default.
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