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• W2103306204 abstract "In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for power grid analysis rely on a model of representing the transistor network as a current source. The disadvantage of the above model is that the drain capacitance of the PMOS transistors which are already on is not modeled. The drain capacitance of the PMOS transistors which are on, act much like a decoupling capacitance in the power grid. By ignoring the drain capacitance, the voltage drop predicted is pessimistic. This implies that a designer is likely to overestimate the amount of decoupling capacitance needed. In our proposed model, we model the transistor network as a simple switch in series with a RC circuit. The presence of switches leads to a non-constant conductance matrix. So, the switch is modeled behaviorally to make the conductance matrix a constant in presence of switches. The resulting conductance matrix is a M-matrix thus making it amenable to linear algebraic methods presented in the literature. The proposed model is nearly as accurate as the SPICE model in predicting the voltage drop. We demonstrate that the current source model of the transistor network has an error of about 10% in predicting the voltage drop. The proposed model offers the middle ground between the accuracy of SPICE simulation and the speed of the current source model. The proposed model is 20--30x faster than SPICE. It also reduces the size of the decoupling capacitance by 2--10x in comparison with the methods presented in the literature." @default.
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• W2103306204 date "2007-01-01" @default.
• W2103306204 modified "2023-10-16" @default.
• W2103306204 title "Accurate power grid analysis with behavioral transistor network modeling" @default.
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• W2103306204 doi "https://doi.org/10.1145/1231996.1232007" @default.
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