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- W2103310453 abstract "Degradation mechanisms of poly-Si N-type TFT due to ESD stress are reported employing TLP (Transmission Line Pulser) test. ESD pulse generated by TLP is applied on the drain and the gate of poly-Si TFT. Experimental results show that degradations caused by ESD stress on the drain are classified into three different failure modes depending on the strength of ESD stress; degradation regime, partial failure regime and complete failure regime. ESD stress on the gate results in the shift of the threshold voltage (V TH ), the decrease of on-current and the increase of off-current. ESD stress on the gate of poly-Si TFT increases the gate oxide fixed trap charge s, which is verified by C-V measurements." @default.
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- W2103310453 date "2002-10-01" @default.
- W2103310453 modified "2023-10-18" @default.
- W2103310453 title "ESD degradation analysis of poly-Si N-type TFT employing TLP (Transmission Line Pulser) test" @default.
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