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- W2103452556 abstract "The current generation of digital-signal-processing (DSP) chips is able to handle regular arithmetic operations in an efficient way but has problems with decision-making irregular algorithms. The reason is that decisions are taken by branching in the microcode, and the efficiency of these branches is limited by pipelines in the controller. The author looks for controller architectures that allow much more efficient implementations of decision-making algorithms. These architectures will be used as target architectures in a silicon compilation environment. Therefore they have to be flexible and parametrizable such that they can be adapted to the requirements of a particular application. >" @default.
- W2103452556 created "2016-06-24" @default.
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- W2103452556 date "2003-01-06" @default.
- W2103452556 modified "2023-09-23" @default.
- W2103452556 title "Efficient controller architectures for DSP compilers" @default.
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- W2103452556 doi "https://doi.org/10.1109/cicc.1988.20867" @default.
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