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• W2103704612 abstract "Hardware support for floating-point (FP) arithmetic is a mandatory feature of modern microprocessor design. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important in many modern applications. Therefore, overall performance can be greatly affected by the algorithms and the implementations used for designing FP-Div and FP-Sqrt units. In this paper, a single-precision fused floating-point multiply/divide/square root unit based on Taylor-series expansion algorithm is proposed. We extended an existing multiply/divide fused unit to incorporate the square root function with little area and latency overhead since Taylor's theorem enables us to compute approximations for many well-known functions with very similar forms. The implementation results of the proposed fused unit based on standard cell methodology in IBM 90 nm technology exhibits that the incorporation of square root function to an existing multiply/divide unit requires only a modest 18% area increase and the same low latency for divide and square root operation can be achieved (12 cycles). The proposed arithmetic unit exhibits a reasonably good area-performance balance." @default.
• W2103704612 created "2016-06-24" @default.
• W2103704612 creator A5036528797 @default.
• W2103704612 creator A5037825309 @default.
• W2103704612 date "2009-11-01" @default.
• W2103704612 modified "2023-10-16" @default.
• W2103704612 title "Floating-point division and square root using a Taylor-series expansion algorithm" @default.
• W2103704612 cites W1971026607 @default.
• W2103704612 cites W1999193585 @default.
• W2103704612 cites W2100502275 @default.
• W2103704612 doi "https://doi.org/10.1016/j.mejo.2009.03.004" @default.
• W2103704612 hasPublicationYear "2009" @default.
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