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- W2104436719 abstract "The RACE parallel computer system provides a high-performance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE system, a parallel computer for embedded applications. The topology of the network, which is constructed with 6-port switches, can be specified by the customer and is typically a fat-tree, a Clos network, or a mesh. The network employs a preemptable circuit switched strategy. The network and the processor-network interface work together to provide high performance: 160 megabytes per second transfer rates with about 1 microsecond of latency. Priorities can be used to guarantee tight real-time constraints of a few microseconds through a congested network. A self-regulating circuit adjusts the impedance and output delay of the pin-driver pads. >" @default.
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- W2104436719 date "2002-11-19" @default.
- W2104436719 modified "2023-09-30" @default.
- W2104436719 title "The RACE network architecture" @default.
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- W2104436719 doi "https://doi.org/10.1109/ipps.1995.395978" @default.
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