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- W2104947964 abstract "Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved. >" @default.
- W2104947964 created "2016-06-24" @default.
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- W2104947964 date "2002-12-04" @default.
- W2104947964 modified "2023-09-28" @default.
- W2104947964 title "Reliability, testability and yield of majority voting VLSI" @default.
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- W2104947964 doi "https://doi.org/10.1109/asic.1990.186155" @default.
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