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• W2105211230 abstract "Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of resource- and timing constraints. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing, resource and register constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules with low register requirements." @default.
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• W2105211230 date "1998-02-23" @default.
• W2105211230 modified "2023-09-23" @default.
• W2105211230 title "A constraint driven approach to loop pipelining and register binding" @default.
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• W2105211230 doi "https://doi.org/10.5555/368058.368187" @default.
• W2105211230 hasPublicationYear "1998" @default.
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