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- W2105231259 abstract "Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable. In practice, however, designers avoid these constructs because it is difficult to understand and predict the properties of the generated code. Is the generated code even type safe? Is it synthesizable? What physical resources (e.g. combinatorial gates and flip-flops) does it require? It is often impossible to answer these questions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration." @default.
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- W2105231259 date "2008-01-07" @default.
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- W2105231259 title "Synthesizable high level hardware descriptions" @default.
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- W2105231259 doi "https://doi.org/10.1145/1328408.1328416" @default.
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