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- W2105363335 abstract "Techniques are described which are used by Intel's standard cell place and route system to achieve dense, high-performance results. The system uses a two-step approach to achieve high performance: first reduce the average path length by producing a dense result, and then adjust the result to reduce delay on the slowest paths. The performance improvement process involves interaction between the layout tool and some of Intel's performance verification tools. >" @default.
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- W2105363335 date "2002-12-04" @default.
- W2105363335 modified "2023-09-26" @default.
- W2105363335 title "Synthesis for high performance random logic layout" @default.
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- W2105363335 doi "https://doi.org/10.1109/iscas.1990.112230" @default.
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