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- W2105880860 abstract "A new approach to modeling the decoding hierarchy in a hierarchical word line (HWL) SRAM architecture using integer-linear programming (ILP) is introduced. Using this approach, the HWL architecture is shown to be inadequate for very large SRAM sizes. Alternatively, a new low-power high-speed SRAM architecture is described. This architecture is shown to have fairly constant speed and power dissipation for sizes ranging between 32 kb to 4 Mb. Low-power is achieved by a voltage boosting technique not requiring a two-step voltage and by a new method of tristating memory cells during a write operation. The SRAM was implemented in a 0.35 /spl mu/m CMOS technology operated at 150 MHz while dissipating only 10 mW." @default.
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- W2105880860 date "2002-11-27" @default.
- W2105880860 modified "2023-09-27" @default.
- W2105880860 title "A low-power high-performance embedded SRAM macrocell" @default.
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- W2105880860 doi "https://doi.org/10.1109/glsv.1998.665192" @default.
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