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- W2105885552 abstract "Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively." @default.
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- W2105885552 date "2005-07-27" @default.
- W2105885552 modified "2023-09-24" @default.
- W2105885552 title "Bitline Leakage Compensation (BLC) and Leakage Reduction (BLR) Techniques for 23GHz On-Chip Cache Arrays in Microprocessors on 90nm Logic Technology" @default.
- W2105885552 doi "https://doi.org/10.1109/vlsic.2005.1469381" @default.
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