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- W2105977039 abstract "We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the critical path latency of a conventional dynamic scheduler is greatly affected by wire delay, we propose 3D-integrated scheduler designs by partitioning a conventional scheduler across multiple vertically-stacked die. The die-stacked organization reduces the lengths of critical wires thus reducing both latency and energy. Our simulation results show that a 20-entry (120-entry) instruction scheduler implemented in a 2-die stack achieves a 9% (19%) reduction in latency with simultaneous energy reduction as compared to a conventional planar design. The benefits are even larger when the instruction scheduler is implemented on a 4-die stack, with the corresponding latency reductions being 12% (32%)." @default.
- W2105977039 created "2016-06-24" @default.
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- W2105977039 date "2006-04-30" @default.
- W2105977039 modified "2023-09-24" @default.
- W2105977039 title "Dynamic instruction schedulers in a 3-dimensional integration technology" @default.
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- W2105977039 doi "https://doi.org/10.1145/1127908.1127946" @default.
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