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- W2106060469 abstract "We are constructing a multiprocessor system for running connectionist simulations, particularly for layered networks. Programmable gate arrays are used to shift data along a communication ring with minimal processor intervention. The initial system is designed with 68 MBytes of memory distributed among an may of 16 floating pint DSP chips, with an aggregate peak performance of 512 MFlops. Expected communication overhead is no moTe than 10-209’0 for algorithms of current interest." @default.
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- W2106060469 date "1989-01-01" @default.
- W2106060469 modified "2023-09-25" @default.
- W2106060469 title "A multi-DSP ring array for connectionist simulations" @default.
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- W2106060469 doi "https://doi.org/10.1109/acssc.1989.1200742" @default.
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