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• W2106264726 abstract "A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>min</sub> to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation." @default.
• W2106264726 created "2016-06-24" @default.
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• W2106264726 date "2009-06-01" @default.
• W2106264726 modified "2023-10-13" @default.
• W2106264726 title "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{min}$ Lowering Techniques and Deep Sleep Mode" @default.
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• W2106264726 doi "https://doi.org/10.1109/jssc.2009.2020201" @default.
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