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- W2106500178 abstract "An 8-bit 800 MS/s time-interleaved pipeline ADC with SNDR of 47.8 dB and 44.2 dB for 1 MHz and 400 MHz inputs is presented. The techniques of sub-ADC preamp sharing and reference voltage buffer current-reusing are proposed to minimize power consumption. The ADC implemented in 65 nm digital CMOS process with an active area of 0.12 mm2 consumes 30 mW from a 1.2 V supply and achieves a FOM of 0.28 pJ/conversion-step." @default.
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- W2106500178 date "2008-06-01" @default.
- W2106500178 modified "2023-09-30" @default.
- W2106500178 title "A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS" @default.
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- W2106500178 doi "https://doi.org/10.1109/vlsic.2008.4585956" @default.
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