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• W2106673654 abstract "<para xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> A 16 Gb 4-state MLC NAND flash memory augments the sustained program throughput to 34 MB/s by fully exercising all the available cells along a selected word line and by using additional performance enhancement modes. The same chip operating as an 8 Gb SLC device guarantees over 60 MB/s programming throughput. The newly introduced All Bit Line (ABL) architecture has multiple advantages when higher performance is targeted and it was made possible by adopting the “current sensing” (as opposed to the mainstream “voltage sensing”) technique. The general chip architecture is presented in contrast to a state of the art conventional circuit and a double size data buffer is found to be necessary for the maximum parallelism attained. Further conceptual changes designed to counterbalance the area increase are presented, hierarchical column architecture being of foremost importance. Optimization of other circuits, such as the charge pump, is another example. Fast data access rate is essential, and ways of boosting it are described, including a new redundancy scheme. ABL contribution to energy saving is also acknowledged. </para>" @default.
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• W2106673654 date "2009-01-01" @default.
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• W2106673654 title "A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology" @default.
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• W2106673654 doi "https://doi.org/10.1109/jssc.2008.2007152" @default.
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