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• W2107060509 abstract "A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy the automatic method for the insertion of self test registers as well as the synthesis of a test control unit is presented. These self testable modules are then combined for arbitrary hierarchy levels using test management units. The concept is embedded within the boundary-scan architecture and the implementation has been integrated into a commercial design framework. >" @default.
• W2107060509 created "2016-06-24" @default.
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• W2107060509 date "2003-01-02" @default.
• W2107060509 modified "2023-09-27" @default.
• W2107060509 title "A methodology for the insertion of a hierarchical and boundary-scan compatible self test" @default.
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• W2107060509 doi "https://doi.org/10.1109/vtest.1992.232721" @default.
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