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- W2108001330 abstract "This paper presents the design and implementation of a CDR (clock and data recovery) design for LVDS transceiver operations. Instead of using an oversampling scheme, which requires a high-speed clock generator, we adopt an interpolation scheme, which relaxes the demand of a high-speed PLL with very high precision. A dual-tracking design is proposed to precisely align both edges of a data eye. Hence, the center of a data eye can be optimally sampled. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7/spl times/100 (bit-MHz) LVDS signaling. The post-layout simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners." @default.
- W2108001330 created "2016-06-24" @default.
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- W2108001330 date "2004-12-23" @default.
- W2108001330 modified "2023-09-27" @default.
- W2108001330 title "Clock recovery and data recovery design for LVDS transceiver used in LCD panels" @default.
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- W2108001330 doi "https://doi.org/10.1109/newcas.2004.1359054" @default.
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